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International Journal of Reconfigurable and Embedded Systems (IJRES)
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 292 Documents
GSM Based Generator Monitoring System for Steel Melting Shop S. Boopathi; M. Jagadeeshraja; L. Manivannan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 1: March 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (525.164 KB) | DOI: 10.11591/ijres.v5.i1.pp42-48

Abstract

Steel making processes are highly energy intensive and comprised of many complex unit operations. Iron ore and coal need preprocessing before feeding into a reactor, and molten metal from different reactors needs to be carefully drawn into a solid metal and then rolled into sheets. Each of these operations has a stake in the quality of steel produced, and needs constant monitoring and need continuous power supply for fabrication. If a power failure occurs the production will be stopped, time delay increases for finishing fabrication. In some cases we can loss consumer due to unsatisfactory. My Project focuses the detection of power failure and takes reflex action to solve the problem with help of modem communication using GSM. The power failure will be intimated to the Microcontroller it drive the GSM modem to send a text message to the concern person mobile number which was already programmed in Microcontroller and also monitoring the parameter are temperature, oil level, fuel level and when they exceed predefined limits an automatically intimated to authorized person and also This system can be designed to send SMS alerts whenever the Circuit Breaker (Relay) trips and simulation result done by using LabVIEW software.
FPGA Implementation of a 64-Bit RISC Processor Using VHDL Imran Mohammad; Ramananjaneyulu K
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (277.105 KB) | DOI: 10.11591/ijres.v1.i2.pp59-66

Abstract

In this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-in-self test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte’s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits, smart phones, ATMs.
Software and Hardware for managing Scratch Pad Memory Chabane Hemdani; Rachida Aoudjit; Mustapha Lalam; Khaled Slimani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 2: July 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (671.72 KB) | DOI: 10.11591/ijres.v6.i2.pp69-81

Abstract

This paper proposes a low-cost architecture to improve the management SPM (Scratch Pad Memory) in dynamic and multitasking modes. In this context, our management strategy SPM based on Programmable Automaton implemented in Xilinx Vertex-5 FPGA is entirely different from prior research works. SPM is generally managed by software (by a strong programming logic or by compilation). But our Programmable Automaton facilitates access to SPM in order to move code or data and liberates space in SPM. After this step, software takes over content management of SPM (what part of code or data should be placed in SPM, locates spaces of Heap and Stack). So the performance of the programs is actually improved thanks to minimization of the access latency at the DRAM (Dynamic Random Access Memory or Main Memory).
Crosstalk Minimization in VLSI Interconnects Damanpreet Kaur; V. Sulochana
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (402.555 KB) | DOI: 10.11591/ijres.v2.i2.pp89-98

Abstract

Crosstalk noise is often induced in long interconnects running parallel to each other .There arises a need to minimize the effect of these crosstalk noise so as to maintain the signal integrity in interconnects. So in this paper crosstalk noise is minimized using various techniques such as repeater (bidirectional buffer) insertion along with shielding, skewing and shielding & skewing simultaneously. With the help of these techniques crosstalk noise is controlled to a great extent in long interconnects. Prelayout simulations for crosstalk are carried out for different techniques at 90nm technology nodes using cadence. The influences of these techniques are analyzed and it is found that crosstalk is reduced upto 57%.
Notice of Retraction Designing of Vedic Based Modulo Multiplication in Residue Number System Shamim Akhter; Divya Bareja; Satyendra Kumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 2: July 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v7.i2.pp67-73

Abstract

Notice of Retraction-----------------------------------------------------------------------After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IAES's Publication Principles.We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.The presenting author of this paper has the option to appeal this decision by contacting ijres@iaesjournal.com.-----------------------------------------------------------------------Residue Number System (RNS) is a very old number system which was proposed in 1500 AD. Parallel nature for mathematical operations in RNS results in faster computation. This paper deals with designing of modulo multiplication in RNS. Direct computation of |AB|m, requires multiplier to get A.B first and then Mod-m calculator to get the final result. We have used Vedic technique along with RNS to improve the computation time for modulo multiplication. This paper is aimed at designing and analysis of modulo multiplier for special moduli set like 3, 5 and 7. Comparative analysis in terms of area and delay is performed for input data size (N=8, 16 and 32-bit) between proposed technique and direct computation using Xilinx ISE 14.1. Design is also been compared using Synopsys Design Compiler with 32 nm Std_Cell Library. It is found that proposed technique is more efficient in terms of speed when input data size increases.
Design and Implementation of an Ethernet MAC IP Core for Embedded Applications Sanket Suresh Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (580.594 KB) | DOI: 10.11591/ijres.v3.i3.pp85-97

Abstract

An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. Ethernet continues to be one of the most popular LAN technologies. Due to the robustness resulting from its wide acceptance and deployment, there has been an attempt to build Ethernet-based real-time control networks for manufacturing automation. There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications. In this paper a project is discussed to design an Ethernet MAC IP Core solution for such embedded applications. The proposed 10_100_1000 Mbps tri-mode Ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependence. To increase the flexibility, three optional modules can be added to or removed from the project. A GUI configuration interface, created by Tcl/tk script language, is convenient for configuring optional modules, FIFO depth and verification parameters. Furthermore, a verification system was designed with Tcl/tk user interface, by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price.
Performance evaluation of embedded ethernet and Controller Area Network (CAN) in real time control communication system Ching Chia Leong; Mohamad Khairi Ishak
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1353.942 KB) | DOI: 10.11591/ijres.v8.i1.pp36-50

Abstract

Real-time communication is important in control network. In real-time communication, message need to be delivered from source to destination within specification. Embedded Ethernet and Controller Area Network (CAN) protocol can be used in control network to achieve hard real-time communication. For embedded Ethernet protocol, Carrier Sense Multiple Access with Collision Detection (CSMA/CD) is the media access control (MAC) used to control data transmission between nodes in network. Back-off algorithm in CSMA/CD is used to handle packet collisions and retransmission. For CAN protocol, it is communication protocol developed mainly for automotive application. It has priority arbitration to handle collisions and retransmission. In this project, embedded Ethernet network models and CAN network models are developed and simulated in MATLAB Simulink software. Several back-off algorithms, which are Binary Exponential Backoff (BEB), Linear Back-off Algorithm, Exponential-Linear back-off Algorithm and Logarithm Back-off Algorithm are proposed and implemented into Embedded Ethernet network model to evaluate the performance. Both embedded Ethernet and CAN network models are extended to 3 nodes, 10 nodes, and 15 nodes to evaluate performance at different network condition. The performance criteria evaluated and discussed are average delay and jitter of packets. The results show that in network with high number of nodes, Linear Back-off Algorithm and Exponential-Linear back-off Algorithm shows improvement in packets delay and jitter. For CAN network, the packet jitter is relatively low.
FPGA Based Controller Area Network Ali Ghareaghaji
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 2: July 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (70.209 KB) | DOI: 10.11591/ijres.v4.i2.pp122-128

Abstract

In this paper the Controller Area Network (CAN) Controller is presented. CAN is an advance serial bus communication protocol that efficiently supports distributed, broadcast real-time control and fault tolerance features for automobile industries to provide congestion free networking. The CAN Controller is designed for scheduling of messages, consist of the Transmitter Controller, FIFO buffer, CRC generator and bit stuffer. Scheduling messages on CAN corresponds to assigning identifiers (IDs) to message according to their priorities. Non Return to Zero (NRZ) coding and Non Destructive Bitwise Arbitration (NDBA) is used. The data is taken from the buffer FIFO, bit stuffed and then transmitted after CRC is performed. The whole design is captured entirely in VHDL language using bottom up design and verification methodology. The proposed controller was designed for applications needing high level data integrity and data rates upto 1Mbps. The applications of CAN are factory automation, machine control, automobile, avionics and aerospace, building automation.
Smart Safety Belt Design to Avoid Accidents in Hazardous Industrial Environment Muhammad Yaseen; Saad Qasim Khan; Muhammad Khurram; Rana N. Mubarak
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 2: July 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (406.012 KB) | DOI: 10.11591/ijres.v5.i2.pp108-114

Abstract

Warehouse is one of the most dangerous places to work because of many potential dangers. The accidents caused by heavy vehicles result in seriousinjuries and even death. This paper proposes a solution to this problem. When a worker happens to be in any of such hazardous situations inside or outside workplace, he will press the emergency button (or pull a magnetic cord) placed in the smart safety belt which will not only stop the vehicles within 15 meters circle but also inform the workers within 250 meters circle through an indicator. In this technical paper, the outcome of first design phase has been reported. In the first design phase, we have successfully implemented a reliable and accurate ranging mechanism with ±0.3m maximum error. This ranging mechanism is based on wellknown RF Time-of-Flight (TOF) method. The maximum achievable transmit range of this solution is 300m.
Performance evaluation of an efficient five input majority gate design in QCA nanotechnology Amanpreet Sandhu; Sheifali Gupta
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 3: November 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (806.525 KB) | DOI: 10.11591/ijres.v8.i3.pp194-205

Abstract

Quantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design.

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