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All Journal International Journal of Electrical and Computer Engineering Perfecting a Video Game with Game Metrics Journal of ICT Research and Applications Communications in Science and Technology
Yusuf Kurniawan
Institut Teknologi Bandung
Computer Science & IT Electrical & Electronics Engineering Engineering

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Revealing AES Encryption Device Key on 328P Microcontrollers with Differential Power Analysis Septafiansyah Dwi Putra; Adang Suwandi Ahmad; Sarwono Sutikno; Yusuf Kurniawan; Arwin Datumaya Wahyudi Sumari
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (838.471 KB) | DOI: 10.11591/ijece.v8i6.pp5144-5152

Abstract

This research demonstrates the revealing of an advanced encryption standard (AES) encryption device key. The encryption device is applied to an ATMEGA328P microcontroller. The said microcontroller is a device commonly used in internet of things (IoT). We measured power consumption when the encryption process is taking place. The message sent to the encryption device is randomly generated, but the key used has a fixed value. The novelty of this research is the creation of a systematic and optimal circuit in carrying the differential power analysis or difference of means (DPA/DoM) technique, so the technique can be applied in key revealing on a microcontroller device by using 500 traces in 120 seconds.
Power analysis attack against encryption devices: a comprehensive analysis of AES, DES, and BC3 Septafiansyah Dwi Putra; Mario Yudhiprawira; Sarwono Sutikno; Yusuf Kurniawan; Adang Suwandi Ahmad
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 17, No 3: June 2019
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v17i3.9384

Abstract

Cryptography is a science of creating a secret message and it is constantly developed. The development consists of attacking and defending the cryptography itself. Power analysis is one of many Side-Channel Analysis (SCA) attack techniques. Power analysis is an attacking technique that uses the information of a cryptographic hardware’s power consumption. Power analysis is carried on by utilizing side-channel information to a vulnerability in a cryptographic algorithm. Power analysis also uses a mathematical model to recover the secret key of the cryptographic device. This research uses design research methodology as a research framework started from research clarification to descriptive study. In this research, power analysis attack is implemented to three symmetrical cryptographic algorithms: DES (Data Encryption Standard), AES (Advanced Encryption Standard), and BC3 (Block Cipher 3). The attack has successfully recovered 100% of AES secret key by using 500 traces and 75% DES secret key by using 320 traces. The research concludes that the power analysis attack using Pearson Correlation Coefficient (PCC) method produces more optimal result compared to a difference of means method.
Diversity Combining Using Maxima Ratio Combining for All Modulation Mode Yusuf Kurniawan; Andyes Fourman D.A. Sudirja
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 12, No 3: September 2014
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v12i3.103

Abstract

The destruction caused by channel can be seen by the existence of Amplitude and Phase Shift. By using the 6 Ways Diversity Combining method (6 Antennas/Receivers), it is expected that the disruption caused by Amplitude and Phase Shift can be suppressed as small as possible. In addition, by using diversity combining module, we will get a large SNR output which has a value sum of SNR of each diversity path. The design of Diversity combining module begins with MATLAB functional design as a big picture of the whole system. Subsequently, it will be made the hardware based on the MATLAB functional. This architectural design that will be the cornerstone in the MATLAB bit precision manufacturing. Then MATLAB bit precision will be designed as the foundation of the VHDL design. Diversity combining the output module meets the standards specified by the DVB consortium. In the hardware (FPGA) test results of diversity combining, the maximum working frequency is 44.56 MHz which has shown that is qualified with the standard sampling clock (9.142 MHz). This design also needs 4% of total FPGA Cyclone II 484I8 combinational units which is 2499 units and it needs also 3% of total register of FPGA Cyclone II 484I8 which is 1720 register units.
Architecture for the Secret-Key BC3 Cryptography Algorithm Arif Sasongko; Hidayat Hidayat; Yusuf Kurniawan; Sarwono Sutikno
Journal of ICT Research and Applications Vol. 5 No. 2 (2011)
Publisher : LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.5614/itbj.ict.2011.5.2.4

Abstract

Cryptography is a very important aspect in data security. The focus of research in this field is shifting from merely security aspect to consider as well the  implementation  aspect.  This  paper  aims  to  introduce  BC3  algorithm  with focus  on  its  hardware  implementation.  It  proposes  an  architecture  for  the hardware  implementation  for  this  algorithm.  BC3  algorithm  is  a  secret-key cryptography  algorithm  developed  with  two  considerations:  robustness  and implementation  efficiency.  This  algorithm  has  been  implemented  on  software and has good performance compared to AES algorithm. BC3 is improvement of BC2 and AE cryptographic algorithm and it is expected to have the same level of robustness and to gain competitive advantages in the implementation aspect. The development of the architecture gives much attention on (1) resource sharing and (2)  having  single  clock  for  each  round.  It  exploits  regularity  of  the  algorithm. This architecture is then implemented on an FPGA. This implementation is three times smaller area than AES, but about five times faster. Furthermore, this BC3 hardware  implementation  has  better  performance  compared  to  BC3  software both in key expansion stage and randomizing stage. For the future, the security of this implementation must be reviewed especially against side channel attack.
Block cipher four implementation on field programmable gate array Yusuf Kurniawan; Muhammad Adli Rizqulloh
Communications in Science and Technology Vol 5 No 2 (2020)
Publisher : Komunitas Ilmuwan dan Profesional Muslim Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.21924/cst.5.2.2020.184

Abstract

Block ciphers are used to protect data in information systems from being leaked to unauthorized people. One of many block cipher algorithms developed by Indonesian researchers is the BCF (Block Cipher-Four) - a block cipher with 128-bit input/output that can accept 128-bit, 192-bit, or 256-bit keys. The BCF algorithm can be used in embedded systems that require fast BCF implementation. In this study, the design and implementation of the BCF engine were carried out on the FPGA DE2. It is the first research on BCF implementation in FPGA. The operations of the BCF machine were controlled by Nios II as the host processor. Our experiments showed that the BCF engine could compute 2,847 times faster than a BFC implementation using only Nios II / e. Our contribution presents the description of new block cipher BCF and the first implementation of it on FPGA using an efficient method.
Co-Authors Adang Suwandi Ahmad Andyes Fourman D.A. Sudirja Arif Sasongko Arwin Datumaya Wahyudi Sumari Hidayat Hidayat Mario Yudhiprawira Muhammad Adli Rizqulloh Sarwono Sutikno Sarwono Sutikno Septafiansyah Dwi Putra