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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
C Bharatiraja
SRM University
Control & Systems Engineering Electrical & Electronics Engineering

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Modelling, Impedance Design, and Efficiency Analysis of Battery Assists PV tied Quasi-Z source inverter T.K.S Sathayanarayanan; M Ramasamy; C Bharatiraja; JL Munda
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 7, No 3: September 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (579.163 KB) | DOI: 10.11591/ijpeds.v7.i3.pp816-825

Abstract

The photovoltaic (PV) power cohort becoming more and more attractive in modern power systems era to meet out the power demand in the globe. Consequently, the extraction of maximum power and reduced power electronics stuff for PV based power generation system research studies are growing continuously to meet out the large power-scale/high-voltage grid-tie demands. In this junction, to improve the efficiency of the existing PV tied Quasi-Z source inverter (QZSI), in this paper the new attempt has proposed here by connecting two batteries across to the QZ capacitors. When a battery connected across each capacitor, this system can deliver power to the load power when the PV panel outputs a variable power with fluctuations. The battery can be charged or discharged without any extra circuit, because of the unique impedance network of QZSI. New PWM techniques and principles are proposed to control the new energy stored QZSI when applied to the PV power system. They can control the inverter output power and manage the battery power simultaneously. The operating principle and power flow of this system are analysed. The Simulated and experimental results through using the planned 0.2-kW prototype validate the proposed analytic model and the design method. In addition, this paper analyzes all of the functioning states for a QZSI and calculates the power loss.
FPGA Based Design and Validation of Asymmetrical Reduced Switch Multilevel Inverter C Bharatiraja; Harshavardhan Reddy; Sunkavalli Satya Sai Suma; N SriRamsai
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 7, No 2: June 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (623.649 KB) | DOI: 10.11591/ijpeds.v7.i2.pp340-348

Abstract

This paper proposes a new Asymmetrical multilevel inverter topology with reduced number of switches. This topology is superior to the existing multilevel inverter (MLI) configurations in terms of lower total harmonic distortion (THD) value and lower cost. The idea incorporates a new module setup comprising of four different voltage sources having voltage output levels in a specific ratio. The proposed topology uses a novel pulse width modulation (PWM) technique (as presented) to control the gating pulses. The operation is simulated using MATLAB/SIMULINK and its results are validated through FPGA Spartan 3 based hardware prototype inverter (using three voltage sources to produce a 7 level output, which may be extended to 15 level). The circuit complexity is drastically reduced and it is suitable for medium and high power applications. THD for the output is quite low when compared with the conventional inverter.
Co-Authors Harshavardhan Reddy JL Munda M Ramasamy N SriRamsai Sunkavalli Satya Sai Suma T.K.S Sathayanarayanan