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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
Lipika Nanda
KIIT University
Control & Systems Engineering Electrical & Electronics Engineering

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A comparative Analysis of Symmetrical and Asymmetrical Cascaded Multilevel Inverter Having Reduced Number of Switches and DC Sources Lipika Nanda; A Dasgupta; U.K. Rout
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 8, No 4: December 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (627.486 KB) | DOI: 10.11591/ijpeds.v8.i4.pp1595-1602

Abstract

As multilevel inverters are gaining increasing importance .New topologies are being proposed in order to achieve large number of levels in output voltage. A simplified MLI topology has been presented with both symmetrical and asymmetrical configurations. This paper represents a comprehensive analysis of above mentioned topology with FFT analysis,switching and conduction losses of the inverter.Hence efficiency at different carrier frequencies has been calculated successfully.Results are verified with simulation studies.Multilevel inverters are currently considered as a better industrial solution for high dynamic performance and power-quality demanding applications, covering a wide power range.
A Comparative Studies of Cascaded Multilevel Inverters Having Reduced Number of Switches with R and RL-Load Lipika Nanda; Abhijit Dasgupta; Ullash Kumar Rout
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 8, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v8.i1.pp40-50

Abstract

Multilevel inverter offers many benefits for high power application compavered to conventional cascaded Multilevel Inverter topology.This paper presents Symmetric CMLI using variable frequency carrier based pulse width modulation techniques. The proposed topology reduces total harmonic distortion and reduced switching losses for seven level inverter. The simulation study of the proposed topology has been carried out in MATLAB/SIMULINK. The main objective of this paper is to achieve number of levels of MLI with reduced number of switches and DC power sources compared to conventional topology.
Co-Authors A Dasgupta Abhijit Dasgupta U.K. Rout Ullash Kumar Rout