A.N. Kasiran
Universiti Tun Hussein Onn Malaysia

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4-level capacitor-clamped boost converter with hard-switching and soft-switching implementations A.N. Kasiran; Asmarashid Ponniran; A.A. Bakar; M.H. Yatim
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 10, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (570.491 KB) | DOI: 10.11591/ijpeds.v10.i1.pp288-299

Abstract

This paper presents parameters analysis of 4-level capacitor-clamped boost converter with hard-switching and soft-switching implementation. Principally, by considering the selected circuit structure of the 4-level capacitor-clamped boost converter and appropriate pulse width modulation (PWM) switching strategy, the overall converter volume able to be reduced. Specifically, phase-shifted of 120° of each switching signal is applied in the 4-level capacitor-clamped boost converter in order to increase the inductor current ripple frequency, thus the charging and discharging times of the inductor is reduced. Besides, volume of converters is greatly reduced if very high switching frequency is considered. However, it causes increasing of semiconductor losses and consequently the converter efficiency is affected. The results show that the efficiency of 2-level conventional boost converter and 4-level capacitor-clamped boost converter are 98.59% and 97.67%, respectively in hard-switching technique, and 99.31% and 98.15%, respectively in soft-switching technique. Therefore, by applying soft-switching technique, switching loss of the semiconductor devices is greatly minimized although high switching frequency is applied. In this study, passive lossless snubber circuit is selected for the soft-switching implementation in the 4-level capacitor-clamped boost converter. Based on the simulation results, the switching loss is approximately eliminated by applying soft-switching technique compared to the hard-switching technique implementation.
Symmetrical and Asymmetrical Multilevel Inverter Structures with Reduced Number of Switching Devices M. H. Yatim; A. Ponniran; M. A. Zaini; M. S. Shaili; N. A. S. Ngamidun; A.N. Kasiran; A. A. Bakar; J.N. Jumadril
Indonesian Journal of Electrical Engineering and Computer Science Vol 11, No 1: July 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v11.i1.pp144-151

Abstract

The purpose of this study is to analyze the operation and design of symmetrical and asymmetrical multilevel inverter structures with reduced number of switching devices. In this study, the term of conventional inverter is defined as a single cascaded inverter. Specifically, the inverter operates in three complete loops and only produces 2-level and 3-level of output voltages. Usually, cascaded structure suffers from the high total harmonic distortion. Thus, by considering multilevel structure of inverter, low total harmonic distortion reduction and voltage stress reduction on switching devices can be archived. Sinusoidal pulse width modulation and modified square pulse width modulation are used as modulation techniques in switching schemes of the designed multilevel inverters. The findings indicate that, the designed multilevel structure cause low total harmonics distortion at the output voltage. Furthermore, the asymmetrical structure is producing the same output voltage levels with reduced number of switching devices compared to the symmetrical structure is experimentally confirmed. The findings show that the total harmonic distortion for 7-level (symmetrical) and 9-level (asymmetrical) are 16.45% and 15.22%, respectively.
Optimization of PFC cuk converter parameters design for minimization of THD and voltage ripple M. A. Z. A. Rashid; A. Ponniran; M. K. R. Noor; J. N. Jumadril; M. H. Yatim; A.N. Kasiran
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 10, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (480.072 KB) | DOI: 10.11591/ijpeds.v10.i1.pp514-521

Abstract

This paper presents the optimization of PFC Cuk converter parameter design for the minimization of THD and voltage ripple. In this study, the PFC Cuk converter is designed to operate in discontinuous conduction mode (DCM) in order to achieve almost unity power factor. The passive components, i.e., inductor and capacitor are designed based on switching frequency and resonant frequency. Nevertheless, the ranges of duty cycle for buck and boost operations are 0<D<0.5 and 0.5<D<1, respectively for the output voltage variation of the converter. The principle of the parameters design optimization is based on the balancing energy compensation between the input capacitor and output inductor for minimization of THD current. In addition, the selection of high output capacitance will minimize the output voltage ripple significantly. A 65 W PFC Cuk converter prototype is developed and experimentally tested to confirm the parameters design optimization principle. The experimental results show that the THD current is reduced to 4.5% from 61.3% and the output voltage ripple is reduced to 7 V from 18 V after parameters optimization are realized. Furthermore, it is confirmed that the output voltage ripple frequency is always double of the input line frequency, 50 Hz and the output voltage ripple is always lower than the maximum input voltage ripple.