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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Haresh A. Suthar
Parul Institute of technology
Economics, Econometrics & Finance

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VHDL Implementation of H.264 Video Coding Standard Haresh A. Suthar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (615.053 KB) | DOI: 10.11591/ijres.v1.i3.pp95-102

Abstract

This Paper contains VHDL implementation of H.264 video coding standard, which is new video coding standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The main goal of the H.264/AVC standardization effort is to enhance compression performance and provision of a “network-friendly” video representation addressing “conversational” (video telephony) and “no conversational” (storage, broadcast, or streaming) applications.H.264 video coder standard is having fundamental blocks like transform and quantization, Intra prediction, Inter prediction and Context Adaptive Variable Length Coding (CAVLC). Each block is designed and integrated to one top module in VHDL.
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