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All Journal Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics
B. Leela Kumari
University college of Engineering, JNTUK
Computer Science & IT Electrical & Electronics Engineering Engineering

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On-chip Generation of Functional Tests with Reduced Delay and Power Hemanth Kumar Motamarri; B. Leela Kumari
Bulletin of Electrical Engineering and Informatics Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (374.888 KB) | DOI: 10.11591/eei.v6i1.570

Abstract

This paper describes different methods  on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications.
On-chip Generation of Functional Tests with Reduced Delay and Power Hemanth Kumar Motamarri; B. Leela Kumari
Bulletin of Electrical Engineering and Informatics Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (374.888 KB) | DOI: 10.11591/eei.v6i1.570

Abstract

This paper describes different methods  on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications.
On-chip Generation of Functional Tests with Reduced Delay and Power Hemanth Kumar Motamarri; B. Leela Kumari
Bulletin of Electrical Engineering and Informatics Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (374.888 KB) | DOI: 10.11591/eei.v6i1.570

Abstract

This paper describes different methods  on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications.
Co-Authors Hemanth Kumar Motamarri