Norlina Paraman
Universiti Teknologi Malaysia

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Reliability of graphene as charge storage layer in floating gate flash memory M. Hilman Ahmad; N Ezaila Alias; Afiq Hamzah; Zaharah Johari; M. S. Z. Abidin; Norlina Paraman; M. L. Peng Tan; Razali Ismail
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 7, No 2: June 2019
Publisher : IAES Indonesian Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (719.767 KB) | DOI: 10.52549/ijeei.v7i2.1170

Abstract

This study aims to investigate the memory performances of graphene as a charge storage layer in the floating gate with difference doping concentration of n-channel and p-channel substrates using Silvaco ATLAS TCAD Tools. The simulation work has been done to determine the performance of flash memory in terms of memory window, P/E characteristics and data retention and have been validated with the experimental work done by other researchers. From the simulation data, the trend of memory window at low P/E voltage is nearly overlapped between simulation and experimental data. The memory window at ±20V P/E voltage for n-channel and p-channel flash memory cell are 15.4V and 15.6V respectively. The data retention for the n-channel flash memory cell is retained by 75% (from 15.4V to 11.6V) whereas for the p-channel flash memory cell is retained by 80% (from 15.6V to 12.5V) after 10 years of extrapolation with -1/1V gate stress which shows that p-channel flash memory cell demonstrates better data retention compared to n-channel flash memory cell.
Impact of Device Parameter Variation on the Electrical Characteristic of N-type Junctionless Nanowire Transistor with High-k Dielectrics Mohammed Adamu Sule; Mathangi Ramakrishnan; Nurul Ezaila Alias; Norlina Paraman; Zaharah Johari; Afiq Hamzah; Michael Loong Peng Tan; Usman Ulllah Sheikh
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 8, No 2: June 2020
Publisher : IAES Indonesian Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (559.064 KB) | DOI: 10.52549/ijeei.v8i2.1277

Abstract

Metallurgical junction and thermal budget are serious constraints in scaling and performance of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). To overcome this problem, junctionless nanowire field-effect transistor (JLNWFET) was introduced. In this paper, we investigate the impact of device parameter variation on the performance of n-type JLNWFET with high-k dielectrics. The electrical characteristic of JLNWFET and the inversion-mode transistor of different gate length (LG) and nanowire diameter (dNW) was compared and analyzed. Different high-k dielectrics were used to get an optimum device structure of JLNWFET. The device was simulated using SDE Tool of Sentaurus TCAD and the I-V characteristics were simulated using Sdevice Tools. Lombardi mobility model and Philips unified mobility model were applied to define its electric field and doping dependent mobility degradation. A thin-film heavily doped silicon nanowire with a gate electrode that controls the flow of current between the source and drain was used. The proposed JLNWFET exhibits high ON-state current (ION) due to the high doping concentration (ND) of 1 x 1019 cm-3 which leads to the improved ON-state to OFF-state current ratio (ION/IOFF) of about 10% than the inversion-mode device for a LG of 7 nm and the silicon dNW of 6 nm. Electrical characteristics such are drain induced barrier lowering (DIBL) and subthreshold slope (SS) were extracted which leads to low leakage current as well as a high ION/IOFF ratio. The performance was improved by introducing silicon dioxide (SiO2) with high-k dielectric materials, hafnium oxide (HfO2) and silicon nitrate (Si3N4). It was found that JLNWFET with HfO2 exhibits better electrical characteristics and performance.
Adaptive random testing with total cartesian distance for black box circuit under test Arbab Alamgir; Abu Khari A’ain; Norlina Paraman; Usman Ullah Sheikh
Indonesian Journal of Electrical Engineering and Computer Science Vol 20, No 2: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v20.i2.pp720-726

Abstract

Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testing as it generates test patterns without using the structural implementation of the circuit under test. However, random testing ignores the importance of previously applied test patterns while generating subsequent test patterns. An improvement to random testing is Antirandom that diversifies every subsequent test pattern in the test sequence. Whereas, computational intensive process of distance calculation restricts its scalability for large input circuit under test. Fixed sized candidate set adaptive random testing uses predetermined number of patterns for distance calculations to avoid computational complexity. A combination of max-min distance with previously executed patterns is carried out for each test pattern candidate. However, the reduction in computational complexity reduces the effectiveness of test set in terms of fault coverage. This paper uses a total cartesian distance based approach on fixed sized candidate set to enhance diversity in test sequence. The proposed approach has a two way effect on the test pattern generation as it lowers the computational intensity along with enhancement in the fault coverage. Fault simulation results on ISCAS’85 and ISCAS’89 benchmark circuits show that fault coverage of the proposed method increases up to 20.22% compared to previous method.