Akbar Kurnia Putra
Jurusan Teknik Elektro, Universitas Diponegoro Semarang Jl. Prof. Sudharto, SH, Kampus UNDIP Tembalang, Semarang 50275, Indonesia

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PERANCANGAN REGISTER DAN MEMORI PADA PROSESSOR RISC 16-BIT DENGAN TEKNOLOGI 600 nm MENGGUNAKAN PERANGKAT LUNAK ELECTRIC Putra, Akbar Kurnia; Riyadi, Munawar Agus; Darjat, Darjat
Transient: Jurnal Ilmiah Teknik Elektro TRANSIENT, VOL. 4, NO. 2, JUNI 2015
Publisher : Universitas Diponegoro

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (247.689 KB) | DOI: 10.14710/transient.4.2.284-288

Abstract

Abstrak Array memori adalah blok penting dalam sistem digital. Array memori biasanya diimplementasikan dalam register dan memori utama dalam prosesor. Sebagian besar ruang dalam sebuah sirkuit terpadu adalah memori. Pertimbangan utama desain SRAM adalah meningkat kecepatan dan mengurangi area layout. Proyek ini bertujuan untuk menciptakan SRAM yang efisien dan kompak. Desain menggunakan Electric untuk desain floorplan dan LT-Spice untuk menguji layout. Teknologi 600 nm digunakan dalam proyek ini. Penelitian ini menghasilkan desain 2 array SRAM berbeda diimplementasikan dalam register dan memori utama prosesor RISC 16 bit. Delapan register 16-bit dengan 3 bit alamat memiliki kecepatan clock 167 MHz dan luas area 1.170 x 2.350,5, atau 247.507,65 μm2. Sedangkan enam puluh empat memori 16-bit dengan 6 bit alamat memiliki kecepatan clock 100MHz dan luas area 4.731,5 x 1.312,5 lamda, atau 558.908,4375 μm2. Kata kunci : SRAM 12T, Register, Memori  Abstract Memory arrays are essential building block in any digital system. Memory arrays are usually  implemented in a register and main memory in a processor. The majority of space taken in an integrated  circuit  is the memory. Key considerations of SRAM design are increased speed and reduced layout area. This project aims to create an efficient and compact SRAM. Design uses Electric for floorplan design and LT-Spice for test the layout. 600 nm technology was used in this project. This research produced design of 2 different SRAM arrays implemented in a register and main memory of RISC 16 bit processor. The eight 16-bit registers with 3 bit addresses have 167MHz clock speed and 1.170 x 2.350,5 lamda, or 247.507,65 μm2 area. While the sixty four 16-bit memorys with 6 bit addresses have 100MHz clock speed and 4.731,5 x 1.312,5 lamda, or 558.908,4375 μm2 large area. Keywords : SRAM 12T, Register, MemoriKeywords : SRAM 12T, Register, Memori
Evaluation of the Regulation Changes on Environment and Forestry in Indonesia Helmi, Helmi; Syam, Fauzi; Nopyandri, Nopyandri; Putra, Akbar Kurnia
Hasanuddin Law Review VOLUME 6 ISSUE 1, APRIL 2020
Publisher : Faculty of Law, Hasanuddin University

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (488.172 KB) | DOI: 10.20956/halrev.v6i1.2290

Abstract

This article aims to examine the correlation between the concept of proper enforcement of the law as stipulated in Article 5 (2) of the 1945 Constitution of Indonesia and the establishment and implementation of government regulation on environment and forestry. This article is a normative legal research with statute, historical, and conceptual approaches. The result shows that proper legal enforcement means two things, namely, establishment and enactment of government regulation by the President and the content of the regulation that does not contradict the law. Failure to comply with the law means the President does not establish or enforce a government regulation as mandated or the content of the regulation is not in line with the law.  If the President does form or enforce the implementation of government regulation, this means that the President violates his oath and promise to uphold the Constitution and to serve the nation. If the content of the regulation contradicts with the law, it can be canceled. In this situation, the government needs to realign the content of existing regulations. The ministry involved in legal drafting is called to oversee the content and follow through with revisions. All party involves in the making of law and regulation, such as the People Representatives, the President, or the Minister, is reminded to carefully formulate a government regulation.
Facility Security Measures at Ujung Jabung Port: a Review in Terms of The International Ship and Port Facility Security Code Farisi, Mochammad; Putra, Akbar Kurnia; Ardianto, Budi; Harahap, Rahayu Repindowaty
Indonesian Journal of International Law
Publisher : UI Scholars Hub

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (473.864 KB)

Abstract

Ujung Jabung is a region located in the District of Sadu at Tanjung Jabung Regency, Jambi Province, Indonesia. The area strategically lies in the Indonesian Archipelagic Sea Lane 1 (ALKI 1), which is the international trading and shipping lane. It brings about an excellent opportunity for economic development in Jambi Province. With this in mind, the Government of Jambi develops the region into a strategic area that includes Ujung Jabung Port. Based on the 2011-2031 Region’s Spatial Plan (RTRW) of East Tanjung Jabung Regency, the regency designed it to be the main port with the name of Samudera Ujung Jabung Port. The international shipping routes at the port are Ujung Jabung-West Asia-East Europe and Ujung Jabung-Southeast Asia-East Asia. Due to its international nature, the construction of Samudera Ujung Jabung Port should follow the international measures on the security of the port, shipping, and facility. As a Member of the International Maritime Organization (IMO), Indonesia is subject to international law. It ratifies the United Nations Convention on Safety on Life at Sea (SOLAS) 1974 and the auxiliary instrument of International Ships and Port Facility Code (ISPS Code). Accordingly, the construction of Samudera Ujung Jabung Port should comply with the international safety standard as written in the ISPS Code.