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All Journal Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics
Rocco Fazzolari, Rocco
University of Rome Tor Vergata
Electrical & Electronics Engineering

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Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures Carlo Cardarilli, Gian; Luca Di Nunzio, Ing.; Fazzolari, Rocco; Giardino, Daniele; Matta, Marco; Re, Marco; Spanò, Sergio; Simone, Lorenzo
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v8i2.1483

Abstract

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The proposed digital delay is based on a new architecture about the Parallel FIR Filter which is used to describe the Parallel Farrow Filter. Such architecture allows to reach very high processing rate with wideband signals and it is suitable to be used along with Time-Interleaved Analog to Digital Converters (TI-ADC).
Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures Cardarilli, Gian Carlo; Nunzio, Luca Di; Fazzolari, Rocco; Giardino, Daniele; Matta, Marco; Re, Marco; Spanò, Sergio; Simone, Lorenzo
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (903.688 KB) | DOI: 10.11591/eei.v8i2.1483

Abstract

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.
Co-Authors Cardarilli, Gian Carlo Gian Carlo Cardarilli, Gian Giardino, Daniele Giardino, Daniele Luca Di Nunzio, Ing. Marco Re, Marco Matta, Marco Matta, Marco Nunzio, Luca Di Simone, Lorenzo Simone, Lorenzo Spanò, Sergio Spanò, Sergio