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International Journal of Reconfigurable and Embedded Systems (IJRES)
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 229 Documents
Development of BSP for ARM9 Evaluation Board Vinayak Pandit K.; Sanket Dessai; Shilpa Chaudhari
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (853.943 KB) | DOI: 10.11591/ijres.v4.i3.pp161-172

Abstract

With an increasing usage of ARM9 core for different kinds of applications ranging from data acquisition to Mobile application, there arises the need for developing ARM9 based board. To bring up this board, board supporting package (BSP) is must. Board supporting package virtualizes the platform hardware so that the different drivers can be ported easily on any hardware. The boot loader is the initial stage of firmware, which initializes the hardware components presents on the board. A universal Bootloader is chosen and is to be customized with respect to target board. In the later section bootloader is interfaced to the kernel which is obtained form an authorized distributor under general purpose license. The customized board specific routines as well drivers are ported onto the hardware. Then the compiled kernel image is ported onto the target board using a debugger and SAM-BA utility. Linux kernel has seen major releases; the basic architecture of the Linux kernel has remained more or less unchanged. The latest 2.6 version of Linux kernel is ported onto target hardware. Kernel support for many architectures and high-end I/O devices gives the independence to choose appropriate hardware for developing system. The bootloader customization is the critical step, which involves a lot of modifications in the header files. BSP components such as bootloader, kernel is compiled using GNU tool chain; obtained image is ported on target using debugger. BSP porting is a very complex task, which required knowledge of hardware and software control sequence and boot strategy of the controller.
Design and Implementation of a New Architecture of a Real-Time Reconfigurable Digital Modulator (DM) Into QPSK, 8-PSK, and 16-PSK on FPGA Walder Andre; Olivier Couillard
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (969.235 KB) | DOI: 10.11591/ijres.v7.i3.pp173-185

Abstract

One of the prerequisites of Electronic Warfare (EW) is to have the means to provide secure point-to-point wireless data and voice communications with other ground stations. New technologies are giving rise to bigger information security threats. This situation illustrates the best the urgency of reducing the development and upgrade time of EW systems. Previous works suggest that digital systems are the best candidates for this purpose and therefore form the backbone of modern Electronic Warfare. Indeed, Digital Modulation (DM) techniques are widely used in modern wireless communication systems. This is largely due to their high resistance to noise and their high transmission capacity that can be achieved through data multiplexing. In this article, a new reconfigurable architecture of a Phase Shift Keying (PSK) modulation is described. The latter can be configured in real time to produce the following modulation schemes: QPSK, 8-PSK, and 16-PSK without having to regenerate the FPGA configuration bits. This action can be done by software via programming or manually using a DIP switch. The proposed design is implemented on the Xilinx xc7k325tfbg900 FPGA using the Genesis 2 development board. The Vivado Physical Design Automation tool indicates a power consumption of 303 mW by the on-chip circuit. The experimental results are in agreement with the simulations.
Design of AES Pipelined Architecture for Image Encryption/Decryption Module Pravin V. Kinge; S.J. Honale; C.M. Bobade
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (85.941 KB) | DOI: 10.11591/ijres.v3.i3.pp114-118

Abstract

The relentless growth of Internet and communication technologies has made the extensive use of images unavoidable. The specific characteristics of image like high transmission rate with limited bandwidth, redundancy, bulk capacity and correlation among pixels makes standard algorithms not suitable for image encryption. In order to overcome these limitations for real time applications, design of new algorithms that require less computational power while preserving a sufficient level of security has always been a subject of interest. Here Advanced Encryption Standard (AES),as the most widely used encryption algorithm in many security applications. AES standard has different key size variants, where longer bit keys provide more secure ciphered text output. The available AES algorithm is used for  data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to Pipelined AES algorithm through Textio, to obtain the encrypted image. and the encrypted image is the input to Pipelined AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit Pipelined AES algorithm for image encryption and decryption, also to compare the latency , efficiency, security, frequency & throughput . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language.
Impacts of Embedded Generation on Distribution Network Behavior Puladasu Sudhakar; Sushama Malaji; B. Sarvesh
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 2: July 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (338.512 KB) | DOI: 10.11591/ijres.v7.i2.pp91-103

Abstract

This paper explores the impacts of multiple embedded generators penetration on distribution system behavior. For this rationale, a IEEE-13 bus distribution feeder was modeled and investigates by assimilating different types of embedded generation (EG) sources. Different scenarios were implemented in which WIND, SOFC FUEL CELL, SOLAR and MICRO TURBINE plants were modeled with high variability of load and generation to observe their impacts on system’s protection, unsymmetrical faults also consider observing impacts effectively. To eradicate the impacts on distribution system with presence of EG’s and distribution system undergone in the event of faults, in this paper primarily reverse power due to EG integration is estimated and sensed with reverse power relay, Further two types of Superconducting Fault Current Limiters Passive resonance CB (PRCB) SFCL and Inverse current injection CB (I-CB are proposed and results are compared for amended solution in mitigating fault current magnitude and over voltages, Finally penetrations levels are computed mathematically and All the modeling and simulations were carried out using MATLAB SIMULINK tool.
Attendance Logging In Webserver Using Multi Node Embedded System Connected Through Wi-Fi Mohammed Bilal
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (91.637 KB) | DOI: 10.11591/ijres.v1.i3.pp103-107

Abstract

In the present age, we are in need of fully automated attendance logging system. The design of Remote Attendance Logging System and its control is a challenging part.  RFID reader reads the RFID tag, and the details of the tag is logged in the embedded system. The Web based distributed measurement and control is slowly replacing parallel architectures due to its non-crate architecture which reduces complexities. A new kind  of expandable, distributed large attendance logging system based on ARM Cortex M3  boards has been investigated and developed in this paper, whose hardware boards use 32-bit RISC processor with wifi dongle attached to its USB port, and software platform use Keil MDK-ARM for firmware and   HTML for man machine interface.  This system can display date and time of log in and log out of a person. The data can be displayed on web pages at different geographical locations, and at the same time can be transmitted to a Remote Data Acquisition System by using HTTP protocol.  The embedded board can act as a central CPU to communicate between web servers automatically.
Efficient robust speech recognition with empirical mode decomposition using an FPGA chip with dual core Shing-Tai Pan; Ching-Fa Chen; Wen-Sin Tseng
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (871.757 KB) | DOI: 10.11591/ijres.v9.i2.pp109-115

Abstract

The purpose of this paper is to accelate the computing speed of Empirical Mode Decomposition (EMD) based on multi-core embedded systems for robust speech recognition. A reconfigurable chip, Field Programmable Gate Array (FPGA), is used for the implementation of the designed system. This paper applies EMD to discompose some noised speech signals into several Intrinsic Mode Functions (IMFs). These IMFs will be combined to recover the original speech by multiplying their corresponding weights which were trained by Genetic Algorithms (GA). After applying Empirical Mode Decomposition (EMD), we obtain a cleaner speech for recognition. Due to the complexity of the computation of the EMD, a dual-core architecture of embedded system on FPGA is proposed to accelerate the computing speed of EMD for robust speech recognition. This will enhance the efficiency of embedded speech recognition system.
FAST LOCAL FLOW-BASED METHOD USING PARALLEL MULTI-CORE CPUS ARCHITECTURE Moneim, Wafaa Abdel; Salem, Rashed; Hassan, Mohamed
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i3.pp%p

Abstract

Large graphs are available in everywhere such as social networks, chemistry, web link analysis, biology, image processing, and computer networks. Traditional methods of clustering are not suitable to solve this problem due to the computation is very costly. This problem is solved by local graph clustering using a given vertex set as input without working on the complete graph to detect a good cluster. SimpleLocal is introduced and analyzed for locally-biased graph-based learning. This algorithm detects a best conductance cuts close to seed vertices set. In this paper, a new Parallel SimpleLocal (PSL) system is proposed using multi-core CPUs. OMP parallel library is utilized to parallelize the first and second stages of 3StageFlow algorithm where the SimpleLocal algorithm is used it for enhancing the runtime. The experiments are performed on two applications which are image segmentation and community detection. From the experiments, the proposed method improves the runtimes with 72.75% using 4-cores and 81.01% when using 8-cores over the sequential single core
Design and implementation of CNTFET based ternary 1x1 memories S.Tamil Selvan; M. Sundararajan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 3: November 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (611.562 KB) | DOI: 10.11591/ijres.v8.i3.pp175-184

Abstract

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.
FPGA Implementation of Automatic Irrigation and Pesticide Control System D. Hanitha; B. Anusha; M. Durga Prakash
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (382.056 KB) | DOI: 10.11591/ijres.v5.i3.pp132-136

Abstract

In many parts of the world rainfalls are inadequate to meet agricultural needs of farmers. It thus becomes imperative to use an irrigation system that meets the moisture needs of plants in order to increase food crop production. The system described here monitors the moisture and pesticide control needs of crops. Irrigation control is monitored through suitable moisture sensors and automatically pumps water when the need arises through FPGA control logic thus requiring minimal human interventions. We can also use this system for liquid pesticide supply through the selection. Thus, we achieve the efficient supply of water and pesticide as needed by plants and conserve quantity, energy and time. In this paper, the proposed system is designed using Verilog and implemented on FPGA. The system operation is also explained in DSCH (Digital Schematic) software. The system is very simple to operate and ideally suits the irrigation and pesticide need for green houses as well as farms.
VHDL Implementation of H.264 Video Coding Standard Haresh A. Suthar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (615.053 KB) | DOI: 10.11591/ijres.v1.i3.pp95-102

Abstract

This Paper contains VHDL implementation of H.264 video coding standard, which is new video coding standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The main goal of the H.264/AVC standardization effort is to enhance compression performance and provision of a “network-friendly” video representation addressing “conversational” (video telephony) and “no conversational” (storage, broadcast, or streaming) applications.H.264 video coder standard is having fundamental blocks like transform and quantization, Intra prediction, Inter prediction and Context Adaptive Variable Length Coding (CAVLC). Each block is designed and integrated to one top module in VHDL.

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