International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
292 Documents
<![CDATA[High Speed Area Efficient FPGA Implementation of AES Algorithm ]]>
<![CDATA[P. B. Mane]]>;
<![CDATA[A. O. Mulani]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v7.i3.pp157-165
<![CDATA[Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.]]>
<![CDATA[An Integrated Architectural Clock Implemented Memory Design for Embedded System ]]>
<![CDATA[Ravi Khatwal]]>;
<![CDATA[Manoj Kumar Jain]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 2: July 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i2.pp129-141
<![CDATA[Recently Low power custom memory design is the major issue for embedded designer. Micro wind and Xilinx simulator performs efficient cache simulation and high performances with low power consumption. SRAM efficiency analyzed with 6-T architecture design and analyzed the simulation performance for specific application. We have implemented clock based memory architecture design and analyzed internal clock efficiency for SRAM. Architectural clock implemented memory design that reduces access time and propagation delay time for embedded devices. Internal semiconductor material improvement increases simulation performance and these design implemented for application specific design architecture.]]>
<![CDATA[Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD ]]>
<![CDATA[J. Vijay Kumar]]>;
<![CDATA[B. Naga Raju]]>;
<![CDATA[M. Vasu Babu]]>;
<![CDATA[T. Ramanjappa]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 2: July 2016 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v5.i2.pp115-120
<![CDATA[This article represents the implementation of low power pipelined 64-bit RISC processor on Altera MAXV CPLD device. The design is verified for arithmetic operations of both fixed and floating point numbers, branch and logical function of RISC processor. For all the jump instruction, the processor architecture will automatically flush the data in the pipeline, so as to avoid any misbehavior. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. The simulation results have been verified by using ModelSim software. The ALU operations and double precision floating point arithmetic operation results are displayed on 7-Segments. The necessary code is written in Verilog HDL.]]>
<![CDATA[Design and Implementation of Reduced Power Energy Efficient Binary Coded Decimal Adder ]]>
<![CDATA[N. Saravanakumar]]>;
<![CDATA[K. Sakthi Sudhan]]>;
<![CDATA[K. N. Vijeyakumar]]>;
<![CDATA[S. Saranya]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 3: November 2019 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v8.i3.pp185-193
<![CDATA[This paper presents a novel architecture for low power energy binary represented decimal addition. The proposed BCD adder uses Binary to Excess Six Converter (BESC) block for constant correction to adjusts binary outputs exceeding 9 to correct decimal values and exploits the inherent advantage of reduced delay and switching, due to elimination of long carry propagation in second stage addition as in conventional design and switching OFF of the BESC block for decimal outputs less than 9. The proposed BESC-BCD adder has been designed using VHDL code and synthesized using Altera Quartus II. Experimental results demonstrates that the proposed decimal adder can lead to significant power savings and delay reduction compared to existing BCD adders which is realised in better power-delay product(PDP) performance. For example the PDP saving of the proposed BESC-BCD adder for a 1 digit and 2 digit addition implementations are 11.6% and 16.05% respectively, compared to the best of the designs used for comparison.]]>
<![CDATA[Design and development of combat robot for military applications ]]>
<![CDATA[Raju Hajare]]>;
<![CDATA[Mallikarjuna Gowda C.P]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp125-132
<![CDATA[In this paper we have developed a combat robot which will assist our commandos to fight against terrorism. With additional weaponry system it can perform other tasks also. Our preliminary aim in this project is to design a combat robot which can be used to handle the unmanned situations like terror attack inside the building where the firing is heavy and the entry of commandos may be difficult. In such situations the combat robot with spy camera, which is controlled through the control room can be sent into the terrorist occupied area. The robot constantly sends the visuals captured through spy camera to the control room. Based on the visuals received from the robot the control room operator can give directions to the robot. This kind of spy robot can also be used in star hotels, shopping malls, jewelry show rooms.]]>
<![CDATA[Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator ]]>
<![CDATA[Tole Sutikno]]>;
<![CDATA[Aiman Zakwan Jidin]]>;
<![CDATA[Auzani Jidin]]>;
<![CDATA[Nik Rumzi Nik Idris]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 1: March 2012 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v1.i1.pp37-42
<![CDATA[Square root calculation is one of the most useful and vital operation in digital signal processing which in recent generations of processors, the operation is performed by the hardware. The hardware implementation of the square root operation can be achieved by different means, but it is very dependent on programmer's sense and ability to write efficient hardware designs. This paper offers universal and shortest VHDL coding of modified non-restoring square root calculator. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The strategy has conducted to implement successfully in FPGA hardware, and offer an efficient in hardware resource, and it is superior.]]>
<![CDATA[Android Based Switch Controlling Technique for LED Bulbs Using Bluetooth/Wi-Fi Technology ]]>
<![CDATA[Munigoti Saikiran]]>;
<![CDATA[Lalith Nagaram Nagarajan]]>;
<![CDATA[Malladi Bharath]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v6.i1.pp48-52
<![CDATA[This paper presents an efficient approach to switch on/off and control the intensity of an LED bulb from a remote place using Android Applications installed in a Smartphone. As LED household bulbs and lights are energy efficient, drop-in replacements for the incandescent lighting found in homes and offices. These lights produce a warm brightness while providing a significant cost savings over traditional lighting. Bluetooth & Wi-Fi modules are used simultaneously as an interface that make connection between Android Application and the LPC2148 controller by which the generated output can be viewed with the help of an LED bulb and control various other devices, based on the availability in particular areas.]]>
<![CDATA[A Novel Evolutionary Method for Designing Optimized Multifunctional Logic Modules ]]>
<![CDATA[Mehdi Anjomshoa]]>;
<![CDATA[Ali Mahani]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v2.i2.pp55-63
<![CDATA[In this paper, we proposed a novel heuristic method based on Imperialist competitive Algorithm (ICA) to design combinational logic modules which performing different arithmetic functions. According to conventional methods, for multi functional circuit, a distinct circuit is designed for each specific function and then all of them are combined together with multiplexer(s) to have desired circuit. But in our proposed method the whole circuit structure is designed and optimized in one procedure by ICA Algorithm. We tried to optimize the area of circuit by reducing the number of transistors forming logic gates. Simulation results show that our method significantly reduces the number of transistors and gates and accordingly the circuit area.]]>
<![CDATA[Minimizing the loses of solar power generation by designing an intelligent tracking system implemented on FPGA ]]>
<![CDATA[Alaa Hamza Omran]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 3: November 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v6.i3.pp169-178
<![CDATA[The increasing of using of an electrical power as a power source in a large number of devices can occur a serious problem in our daily life. One of the useful power sources is a solar cell which used to overcome many problems of power generation. In this paper, the solar cell model is proposed to minimize loses of solar power generation by designing of an intelligent tracking system based on FPGA. PSO algorithms are used to train the neural networks to control the speeds and the directions of rotations of two DC motors with the help of FPGA cart. The proposed system was implemented in MATLAB; and for the hardware part, FPGA was used for the implementation of neural networks.]]>
<![CDATA[Design of AES Algorithm for 128/192/256 Key Length in FPGA ]]>
<![CDATA[Pravin V. Kinge]]>;
<![CDATA[S.J. Honale]]>;
<![CDATA[C.M. Bobade]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 2: July 2014 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v3.i2.pp49-53
<![CDATA[The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. The available AES algorithm is used for data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to AES algorithm, to obtain the encrypted image. and the encrypted image is the input to AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit AES algorithm for data encryption and decryption, also to compare the speed of operation, efficiency, security and frequency . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language (VHDL).]]>
