Bulletin of Electrical Engineering and Informatics
Vol 8, No 4: December 2019

Comparative performance evaluation of routing algorithm and topology size for wireless network-on-chip

Asrani Lit (Universiti Malaysia Sarawak)
M. S. Rusli (Universiti Teknologi Malaysia)
M. N. Marsono (Universiti Teknologi Malaysia)



Article Info

Publish Date
01 Dec 2019

Abstract

Wireless Network-on-Chip or WiNoC is an alternative to traditional planar on-chip networks. On-chip wireless links are utilized to reduce latency between distant nodes due to its capability to communicate with far-away node within a single hop. This paper analyzes the impact of various routing schemes and the effect of WiNoC sizes on network traffic distributions compared to conventional mesh NoC. Radio hubs (4×4) are evenly placed on WiNoC to analyze global average delay, throughput, energy consumption and wireless utilization. For validation, three various network sizes (8×8,   16×16 and 32×32) of mesh NoC and WiNoC architectures are simulated on cycle-accurate Noxim simulator under numerous traffic load distributions. Simulation results show that WiNoC architecture with the 16×16 network size has better average speedup (∼1.2×) and improved network throughputs by 6.36% in non-uniform transpose traffic distribution. As the trade-off, WiNoC requires 63% higher energy consumption compared to the classical wired NoC mesh.

Copyrights © 2019






Journal Info

Abbrev

EEI

Publisher

Subject

Computer Science & IT Electrical & Electronics Engineering Engineering

Description

Bulletin of Electrical Engineering and Informatics ISSN: 2302-9285 is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication, computer engineering, computer science, information technology and informatics from the global ...