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Vol 16, No 1: February 2018

Asymmetrical Nine-Level Inverter Topology with Reduce Power Semicondutor Devices

M. S. Arif (Universiti Teknologi Malaysia)
S.M. Ayob (Universiti Teknologi Malaysia)
Z. Salam (Universiti Teknologi Malaysia)



Article Info

Publish Date
01 Feb 2018

Abstract

In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is capable of producing nine-level output voltage with reduce device counts. It can be achieved by arranging available switches and dc sources in a fashion such that the maximum combination of addition and subtraction of the input dc sources can be obtained. To verify the viability of the proposed topology, the circuit model is developed and simulated in Matlab-Simulink software. Experimental testing results of the proposed nine-level inverter topology, developed in the laboratory, are presented. A low frequency switching strategy is employed in this work. The results show that the proposed topology is capable to produce a nine-level output voltage, capable in handling inductive load and yields acceptable harmonic distortion content

Copyrights © 2018






Journal Info

Abbrev

TELKOMNIKA

Publisher

Subject

Computer Science & IT

Description

Submitted papers are evaluated by anonymous referees by single blind peer review for contribution, originality, relevance, and presentation. The Editor shall inform you of the results of the review as soon as possible, hopefully in 10 weeks. Please notice that because of the great number of ...