International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
292 Documents
<![CDATA[DESIGN AND IMPLEMENTATION OF AMBIENT NOISE CANCELLATION SYSTEM USING ADAPTIVE FILTERS AND EQUALIZATION TECHNIQUES FOR SIGNAL PROCESSING APPLICATIONS ]]>
<![CDATA[Hajare, Raju]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp%p
<![CDATA[Signal Processing is very important as it gives us the flexibility of using same hardware Processing capabilities to different applications. Aim here is to design a Noise Cancellation system that uses adaptive filter techniques to eliminate any low frequency noise from the environment, leaving the music to play from the headphones without the noise waves. In the course of achieving this, we identify the original signal and generate the inverse without delay in all directions where noises interact and superimpose. We also demonstrate the approaches that we take on tackling the noise cancellation effects, along with results comparison.]]>
<![CDATA[Real-time Optical-flow Computation for Motion Estimation under Varying Illumination Conditions ]]>
<![CDATA[Julio C. Sosa]]>;
<![CDATA[Roberto Rodríguez]]>;
<![CDATA[Víctor H. García Ortega]]>;
<![CDATA[Rubén Hernández]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 1: March 2012 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v1.i1.pp25-36
<![CDATA[The optical flow approach has emerged as a major technique for estimating object motion in image sequences. However, the obtained results by most optical flow techniques are poor because they are strongly affected by large illumination changes and by motion discontinuities. On the other hand, there have been two thrusts in the development of optical flow algorithms. One has emphasized higher accuracy; the other faster implementation. These two thrusts have been independently pursed, without addressing the accuracy vs. efficiency trade-offs. The optical flow computation requires high computing resources and is highly affected by changes in the illumination conditions in most of the existing techniques. In this paper, a new strategy for image sequence processing is proposed. The data reduction achieved with this strategy allows a faster optical flow computation. In addition, the proposed architecture is a hardware custom implementation in EP1S60F1020 FPGA showing the achieved performance.]]>
<![CDATA[Design and Development of IP for Modified Haar Wavelet Transform (MHWT) Image Fusion using FPGA ]]>
<![CDATA[Sumant S Yaliagr]]>;
<![CDATA[Sanket Dessai]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v7.i1.pp57-66
<![CDATA[The fast growth in the field of digital imaging applications in remote sensing, bio medical and other satellite applications had created an architecture studies for image fusion in capable to store large amount of data and process. An algorithm considered for the process of image fusion for implementation of FPGA is Modified Haar Wavelet Transform (MHWT) based image fusion where at the time four pixels are consider in calculation of different bands as compared to conventional Haar wavelet based image fusion. The process of modification uses far less memory and computation power. The FPGA implementation of MHWT based image fusion is done on Digilent development board with Spartan 6 series FPGA. The architecture is developed in VHDL. The timing analysis is done and report is obtained for I/O interactions, memory units etc. The architecture is made to run in cosimulation with Simulink. The design is tested with different kinds of images and run successfully. The visual analysis of the resultant fused image is achived and observed.]]>
<![CDATA[New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT) ]]>
<![CDATA[Abderrezak Marzaki]]>;
<![CDATA[V. Bidal]]>;
<![CDATA[R. Laffont]]>;
<![CDATA[W. Rahajandraibe]]>;
<![CDATA[J-M. Portal]]>;
<![CDATA[R. Bouchakour]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 1: March 2013 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v2.i1.pp49-54
<![CDATA[This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages VTH- (low switching voltage) and VTH+ (high switching voltage).]]>
<![CDATA[Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA ]]>
<![CDATA[G. Prasad Acharya]]>;
<![CDATA[M. Asha Rani]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 3: November 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v6.i3.pp160-168
<![CDATA[This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.]]>
<![CDATA[FPGA Evaluation of Reconfigurable Modules With Fault Detection and Repair Technique ]]>
<![CDATA[Pradeep C]]>;
<![CDATA[Radhakrishnan R]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 2: July 2014 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v3.i2.pp39-48
<![CDATA[This paper proposes a fault detection and repair algorithm which is suitable for fault free reconfigurable systems. In recent years Built in Self Repair digital systems have got very important role in the applications such as nuclear systems, space missions and communication systems etc where system reliability is very critical . Systems designed to operate in critical conditions will collapse due to even a single fault occurrence. To avoid these situations many methods have developed in recent years. This work proposes an area efficient and fast fault detection and repair algorithm. For the evaluation of the new approach and older methods a system with a standalone module and four add on modules were designed and evaluated for resource utilization using XUPV5 board. The entire FPGA is divided in to tiles and each module is implemented in different tiles using partial reconfiguration method using Xilinx Plan Ahead 14.2 with partial reconfiguration facility.]]>
<![CDATA[Secured smart ATM transaction ]]>
<![CDATA[C. R. Balamurugan]]>;
<![CDATA[K. Ramash kumar]]>;
<![CDATA[A. Thirumalai]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v8.i1.pp61-74
<![CDATA[The objective of this paper is to reduce the service tax during mobile transactions. To improve the security and to make the process easy and less time consuming this process is rendered with the help of GSM (Global System for Mobile communication), finger print sensors, PIC16F877A microcontroller and aadhaar number.]]>
<![CDATA[Design and Implementation of Multichannel Data Acquisition and Processing System Using LabVIEW ]]>
<![CDATA[Dhruva R. Rinku]]>;
<![CDATA[Gundu Srinath]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 2: July 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i2.pp55-62
<![CDATA[The data acquisition and processing architecture covers the most demanding applications of continuousmonitoring in industrial field. The multichannel data acquisition is essential for acquiring and monitoring the various signals from industrial sensors. The problem is that the data storage and hardware size, so the multichannel data obtained is processed at runtime and stored in an external storage for future reference. The method of implementing the proposed design is by using the ARM Cortex M-3 Processor to reduce the hardware size. The Cortex M-3 attains high resolution. A Eight channel data acquisition processing (DAQP) and Controlling was designed, developed using the Lab VIEW graphical programming. The module was designed in order to provide high accuracy, storage and portability. The system designed is not specific for any sensor acquisition, so any sensor having signal conditioning circuit built can be connected to the DAQ (Data Acquisition System). ARM controller is used as heart of the DAQ.]]>
<![CDATA[Performance optimization of task intensive real time applications on multicore ECUs - a hybrid scheduler ]]>
<![CDATA[Geetishree Mishra]]>;
<![CDATA[Rajeshwari Hegde]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v8.i2.pp114-123
<![CDATA[In the current approach of Automotive electronic system design, the multicore processors have prevailed to achieve high computing performance at low thermal dissipation. Multicore processors offer functional parallelism that helps in meeting the safety critical requirements of vehicles. The number of ECUs in high-end cars could be reduced by conglomerating more functions into a multicore ECU. AUTOSAR stack has been designed to support the applications developed for multicore ECUs. The real challenges lie in adapting new design methods while developing sophisticated applications with multicore constraints. It is imperative to utilize the most of multicore computational capability towards enhancing the overall performance of ECUs. In this context the scheduling of the real time multitasking software components by the operating system is one of the key issues to be addressed. In this paper, the state of the art scheduling algorithm is reviewed and its merits and limitations are identified. A hybrid scheduler has been proposed, tested and compared with the state of the art algorithm that offers better performance in terms of CPU utilization, average response time and deadline missing rate both in normal and high load conditions.]]>
<![CDATA[Fast, Intelligent and Secure an Embedded Health-care Supervisory System ]]>
<![CDATA[Neha Shivaji Bidgar]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 2: July 2016 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v5.i2.pp75-82
<![CDATA[The world of medical supervisory system should remotely monitor various parameters of patients with help of electronics. This work aims at monitoring parameters in fast, intelligent and secure way. The work emphasizes on designing an embedded system which handles critical parameters of patients in hospital/nursing units. The data samples are processed using an ARM based CPU’s and to achieve performance metrics TI RTOS is used and validated. The system generates interrupts based on the priority of each of critical parameters with a threshold in it and enables alarming/warning system. The data is then transferred to IoT layer using a CC3100 TI based SoC for further reference and processing.In this paper, 4 parameters has been monitored for designing system such as measuring Respiratory rate for human breath, MMG signal for muscle movement, Blood pressure rate as well as Temperature. RTOS helps with scheduling as well as with interrupts also helps Wi-Fi module to work with it. Wi-Fi module provides many security options as WEP, WAP, and WAP2.]]>
