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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
V. Arun
Arunai Engineering College
Control & Systems Engineering Electrical & Electronics Engineering

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Analysis of Binary DC Source Reduced Switch 7-level Inverter V. Arun; B. Shanthi; M. Arumugam
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 6, No 1: March 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (172.574 KB) | DOI: 10.11591/ijpeds.v6.i1.pp70-76

Abstract

This paper proposes a binary DC source reduced switch 7-level inverter. Binary DC source reduced switch inverter is triggered by the Unipolar PWM strategy having sinusoidal and trapezoidal reference with triangular carriers. These Pulse Width Modulating (PWM) strategies include Phase Disposition (PD), Alternate Phase Opposition Disposition (APOD), Carrier Overlapping (CO). Performance factors like Total Harmonic Distortion (THD), VRMS (fundamental) and crest factor are evaluated for various modulation indices. Simulations were performed using MATLAB-SIMULINK. It is observed that UPDPWM strategy with trapezoidal reference provides output with relatively low distortion and UCOPWM strategy with trapezoidal reference provides relatively higher fundamental RMS output voltage.
Co-Authors B. Shanthi M. Arumugam