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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
Umashankar S
VIT University
Control & Systems Engineering Electrical & Electronics Engineering

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A New Multilevel Inverter with Reduced Number of Switches Gnana Prakash; Balamurugan M; Umashankar S
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 5, No 1: 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (316.324 KB)

Abstract

In recent day’s Multilevel inverter (MLI) technologies become a incredibly main choice in the area of high power medium voltage energy control. Though multilevel inverter has a number of advantages it has drawbacks in the vein of higher levels because of using more number of semiconductor switches. This may leads to vast size and price of the inverter is very high. So in order to overcome this problem the new multilevel inverter is proposed with reduced number of switches. The proposed method is well suited for a high power application and it built with three Dc sources and six Switches. Multi carrier pwm technique is used for sine wave generation. The results are validated through the harmonic spectrum of the FFT window by using Matlab/simulink. The result of the proposed MLI is compared with the conventional MLI and other seven level existing topologies.DOI: http://dx.doi.org/10.11591/ijpeds.v5i1.6089
A Novel Topology Of Multilevel Inverter With Reduced Number Of Switches And DC Sources Nakul Thombre; Priyanka Rana; Ratika Singh Rawat; Umashankar S
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 5, No 1: 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (343.265 KB)

Abstract

This paper introduces new topology of cascaded multilevel inverter, with considerable reduction in the number of switches and DC voltage sources. The proposed topology is based on asymmetrical multilevel inverter which produces 21 levels of output with the use of 11 unidirectional switches, 3 diodes and 4 DC voltage sources. The advantages of this topology are reduction in the number of switches (2 nos.) and gate driver circuits (2 nos.), reduction in the number of DC sources (2 nos.) also cost, complexity, and space required for hardware is reduced  without sacrificing the quality output of the inverter. To reduce the THD further Level shifting SPWM techniques such as PD, POD & APOD are used and comparison is shown on the basis of THDs obtained from the above SPWM techniques. Frequency of carrier waves is 1KHz, and modulation index is 1.0. To validate the proposed topology the circuit is simulated and verified by using MATLAB/Simulink.DOI: http://dx.doi.org/10.11591/ijpeds.v5i1.5810
Co-Authors Balamurugan M Gnana Prakash Nakul Thombre Priyanka Rana Ratika Singh Rawat