Garuda - Garba Rujukan Digital

Brahmadeo Prasad Singh

Manipal University Jaipur

Author-ID : 2465164

Computer Science & IT Electrical & Electronics Engineering Engineering

Published : 3 Documents Claim Missing Document

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Articles

Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic Deepika Bansal; Brahmadeo Prasad Singh; Ajay Kumar
Bulletin of Electrical Engineering and Informatics Vol 6, No 2: June 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v6i2.597

The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.

Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic Deepika Bansal; Brahmadeo Prasad Singh; Ajay Kumar
Bulletin of Electrical Engineering and Informatics Vol 6, No 2: June 2017
Publisher : Institute of Advanced Engineering and Science

The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.

Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic Deepika Bansal; Brahmadeo Prasad Singh; Ajay Kumar
Bulletin of Electrical Engineering and Informatics Vol 6, No 2: June 2017
Publisher : Institute of Advanced Engineering and Science

The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.

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