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Kanagasabai Lenin
Department of EEE, Prasad V. Potluri Siddhartha Institute of Technology
Civil Engineering, Building, Construction & Architecture Control & Systems Engineering Electrical & Electronics Engineering Engineering Industrial & Manufacturing Engineering

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ACTIVE POWER LOSS REDUCTION AND IMPROVEMENT OF STATIC VOLTAGE STABILITY MARGIN INDEX BY WATERWAY ALGORITHM Kanagasabai Lenin
SINERGI Vol 22, No 3 (2018)
Publisher : Universitas Mercu Buana

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (212.535 KB) | DOI: 10.22441/sinergi.2018.3.003

Abstract

In this paper, the Waterway Algorithm (WA) is used for Active Power Loss Reduction and improvement of Static Voltage Stability Margin Index. The design of the Waterway Algorithm (WA) is imitated from nature and the whole waterway process which involves the flow of streams and rivers into the sea in the natural world. The proposed Waterway Algorithm (WA) algorithm has been tested on standard IEEE 30 bus test system and simulation results show clearly about the superior performance of the proposed algorithm in reducing the real power loss and upgrading the Static Voltage Stability Margin Index.
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