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All Journal Indonesian Journal of Electrical Engineering and Computer Science
Sara M. Hassan
Modern Academy for Engineering and Technology

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Real time FPGA implemnation of SAR radar reconstruction system based on adaptive OMP compressive sensing Eslam Ashraf; Ashraf A. M. Khalaf; Sara M. Hassan
Indonesian Journal of Electrical Engineering and Computer Science Vol 20, No 1: October 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v20.i1.pp185-196

Abstract

Synthetic aperture radar (SAR) is an imaging system based on the processing of radar echoes. The produced images have a huge amount of data which will be stored onboard or transmitted as a digital signal to the ground station via downlink to be processed. Therefore, some methods of compression on the raw images provides an attractive option for SAR systems design. One of these techniques which used for image reconstruction is the orthogonal matching pursuit (OMP). OMP is an iterative algorithm which need high computational operations. The computational complexity of the iterative algorithms is high due to updating operations of the measurement vector and large number of iterations that are used to reconstruct the images successfully. This paper presents a new adaptive OMP algorithm to overcome this issue by using certain threshold. The new adaptive OMP algorithm is compared with the classical OMP algorithm using the receiver operating characteristic (ROC) curves. The MATLAB simulations show that the new adaptive OMP algorithm improves the probability of detection at lower SNRs, reduce the computational operations as well as the number of required iterations. FPGA implementation of both the classical OMP and the adaptive OMP algorithm are also presented in this paper.
Design and implementation of pipelined and parallel AES encryption systems using FPGA Mohamed Nabil; Ashraf A. M. Khalaf; Sara M. Hassan
Indonesian Journal of Electrical Engineering and Computer Science Vol 20, No 1: October 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v20.i1.pp287-299

Abstract

The information security is one of the most important issues in the design of any communication network.One of the most common encryption algorithms is the advanced encryption standard (AES).The main problem facing the AES algorithm is the high time consumption due to the large number of rounds used for performing the encryption operation. The more time the encryption system consumes to encrypt the data, the more chances the hackers have to break the system.This paper presents two effective algorithms that can be used to solve the mentioned problem and to achieve an effective processing time reduction using pipelined and parallel techniques to perform the encryption steps. These algorithms are based on using certain techniques to make the system able to encrypt many different states (the data will be encrypted) in the same time with no necessity to wait for the previous encryption operation to be completed. These two algorithms are very effective especially for big data size. This paper describes in detail the AES encryption system algorithm and a detailed explanation for the proposed algorithms. Moreover, the research shows the implementation of the three algorithms: the traditional, the pipelined, and the parallel algorithms, and finally a comparison between them.
Real-time FPGA implementation of concatenated AES and IDEA cryptography system Sara M. Hassan; Gihan. G. Hamza
Indonesian Journal of Electrical Engineering and Computer Science Vol 22, No 1: April 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v22.i1.pp71-82

Abstract

The data encryption is one of the most critical issues in the communication system design. Nowadays, many encryption algorithms are being updated to keep pace with the remarkable progress in the communication field. The advanced encryption standard (AES) is a common algorithm that has proved its efficacy. The main drawback of AES is that it uses too simple algebraic structures, since every block is always encrypted in the same way that makes the hacking process possible if the hacker captures the key and the uses S-Box in the input stage. This especially applies to the unwired communication systems where chances of hacking exceed those found in the wired systems. The paper proposes a security enhancement method that is based on utilizing concatenated AES and international data encryption algorithm (IDEA) algorithms. Upon applying the proposed algorithm, the hacking process becomes a great challenge. The paper incorporates the real-time FPGA implementation of the proposed algorithm in the encryption and the decryption stages. Besides, the paper presents a clear analysis of the system’s performance.
Co-Authors Ashraf A. M. Khalaf Ashraf A. M. Khalaf Eslam Ashraf Gihan. G. Hamza Mohamed Nabil