<![CDATA[This paper presents the design of the inter-integrated circuit (I2C) protocol with different types of features, such as combined messages, addressing modes, different data patterns and start addresses, clock frequencies, and types of modes between the field-programmable gate array (FPGA) and test card. Moreover, all these features can be randomized and run for long hours. The FPGA and the test card respectively act as master and slave. The design architecture comprises master and slave. The master generates a START condition, in which the serial data will transact between high to low levels and the serial clock will remain high. Then, the master also generates the STOP condition. Additionally, a few types of messaging modes, such as PIO read, PIO write, PIO write–read, and PIO read–write, are available. By contrast, the master also transfers and receives data to or from slave devices by using different addressing modes. The implemented addressing modes are 7 and 10 bits. This paper also focuses on randomizing the sent data byte and the start address. Particularly, data sending, reading, and writing operations are conducted and stimulated by capturing the signal using a logic analyzer. The signal is then examined and compared with the actual I2C protocol format. A stress test is performed by randomizing all the features and running for long hours (4 h). The stress test aims to stress the IP and ensure the health of IP.]]>
