Article Per Year (5 Year)
p-Index From 2019 - 2024
0.23
P-Index
This Author published in this journals
All Journal Jurnal Pengembangan Teknologi Informasi dan Ilmu Komputer
Anang Malik La Imu
Fakultas Ilmu Komputer, Universitas Brawijaya
Computer Science & IT Control & Systems Engineering Education Electrical & Electronics Engineering Engineering

Published : 1 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 1 Documents
Search

 1 
Implementasi CPU berbasis Simple-As-Possible (SAP) pada FPGA Xilinx Spartan-3E Anang Malik La Imu; Agung Setia Budi; Mochammad Hannats Hanafi Ichsan
Jurnal Pengembangan Teknologi Informasi dan Ilmu Komputer Vol 6 No 5 (2022): Mei 2022
Publisher : Fakultas Ilmu Komputer (FILKOM), Universitas Brawijaya

Show Abstract | Download Original | Original Source | Check in Google Scholar

Abstract

The development of computer technology in the Central Processing Unit (CPU) architecture is still accompanied by many innovations. However, the rapid development has a negative impact, namely the difficulty of participating in the creation of the innovation itself. Meanwhile, the creation of innovations must be carried out by various parties in order to create healthy competition in order to achieve common progress. This impact can be minimized from an educational side, namely in the teaching and learning of computer architecture & organization using software in the form of a simulator. The effectiveness of teaching and learning can be further strengthened by practicing directly (hands-on) an architecture on a programmable semiconductor device, namely the Field Programmable Gate Array (FPGA). There are many soft-processors or computer/CPU architectures that can be implemented on FPGA. Altera and Xilinx also have soft-processors that are ready to use but are not suitable for teaching and learning. This study shows another simple computer architecture that can be used for the focus mentioned, namely Simple-As-Possible (SAP), specifically the 2nd generation. In addition to implementing the SAP architecture with some adjustments, this research also designed two additional circuits to provide the capability for programming the CPU. Three units (including SAP) were implemented on the Xilinx Spartan-3E Starter Kit Board FPGA module. FPGA resource usage are 7% slice flip-flop, 24% 4LUT, 30% slices used, 10% IOB, 5% RAM16 and 4% BUFGMUX.
Co-Authors Agung Setia Budi Mochammad Hannats Hanafi Ichsan