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IMPLEMENTASI PERANGKAT DIGITAL SIGNAL PROCESSING UNTUK SISTEM VISIBLE LIGHT COMMUNICATION Syifaul Fuada; Angga Pratama Putra; Yulian Aska; Angga Pradana; Erwin Setiawan; Trio Adiono
Jetri : Jurnal Ilmiah Teknik Elektro Jetri Volume 15, Nomor 2, Februari 2018
Publisher : Website

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (858.736 KB) | DOI: 10.25105/jetri.v15i2.2352

Abstract

In order to realize a high-speed visible light communication (VLC) system, digital signal processing (DSP) device is required, including the main processing unit, DAC, and ADC. This paper discusses the interface design of the DSP processing unit to 10-bit DAC and 12-bit ADC for VLC applications. The systems in DAC and ADC modules have been designed with a SoC- based approach by using processing unit based on FPGA Xilinx Zynq xc7z010-1CLG400C on the Avnet MicroZed board. The design of hardware-level-design (H/W SoC) is done by utilizing IP blocks from Xilinx using Vivado 2014.2. While the hardware-level-design (S/W SoC) is designed using Xilinx SDK 2014.2. The DSP receiver has been tested in several scenarios, the DAC module is able to convert 10-bit digital signals into analog signals in  sinusoidal form and can adjust its output frequencies, while the ADC module is capable of processing the analog signals into 12-bit digital signals with two's complement format. Keywords: ADC, DAC, DSP, system on-chip, visible light communications Untuk mewujudkan sistem visible light communication dengan kecepatan tinggi, diperlukan perangkat DSP yang memadai, mencakup unit pemroses utama, DAC, dan ADC. Pada makalah ini dirancang interface dari pemroses utama terhadap DAC 10-bit dan ADC 12-bit untuk aplikasi sistem VLC. Sistem pada modul DAC dan ADC, dirancang dengan pendekatan system-on-chip (SoC) dengan menggunakan unit pemroses berbasis FPGA Xilinx Zynq xc7z010-1CLG400C pada board Avnet MicroZed. Perancangan H/W SoC dilakukan dengan memanfaatkan blok-blok IP dari Xilinx menggunakan Vivado 2014.2. Sementara pada S/W SoC dirancang dengan menggunakan Xilinx SDK 2014.2. Penerima DSP telah diuji dengan beberapa skenario, modul DAC mampu mengkonversi sinyal digital 10-bit menjadi analog dalam bentuk sinusiodal dan dapat diatur frekuensi outputnya, sedangkan modul ADC mampu mengolah sinyal analog menjadi sinyal digital 12-bit dengan format bilangan two’s complement. Kata kunci: ADC, DAC, DSP, Sistem on-Chip,visible light communication
Hierarchy Analysis, Leading Commodities and Community Participation in Agropolitan Areas in Trenggalek Regency, East Java Province Angga Pratama Putra; Budi Setiawan; Suhartini Suhartini
HABITAT Vol. 32 No. 2 (2021): August
Publisher : Department of Social Economy, Faculty of Agriculture , University of Brawijaya

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.21776/ub.habitat.2021.032.2.8

Abstract

The agropolitan area in Trenggalek Regency is one of the regional development programs that began in 2006.The objectives of this study are 1) Determining the hierarchical structure of growth and service centers in an agropolitan area, 2) Determining superior commodities that can be developed in an agropolitan area, 3) Knowing perceptions and levels of community participation as well as the factors that influence it in an effort to increase active community participation as the main actor in agropolitan area development. The research location was determined purposively. This study uses two types of data, namely primary data and secondary data. The analytical methods used in this research are 1) scalogram analysis, 2) Location Quotient / LQ analysis, 3) non-parametric chi-square statistical analysis. Based on the schalogram analysis of villages in the agropolitan area in Trenggalek Regency, it is obtained a hierarchy of regions in the agropolitan area in Trenggalek Regency, so that Tasikmadu, Pule, Jombok and Sumurup Villages are the centers of growth and service centers while the development areas of Karanggandu Village, Prigi, Watulimo, Sawahan, Watuagung, Sidomulyo, Tanggaran, and Dompyong are agropolitan areas. While other development areas, namely the Dukuh, Slawe, Gemaharjo, Pakel, Ngembel, Puyung, Joho, Kembangan, Pakel, Masaran, Sengon, Srabah, Surenlor and Botoputih development areas are hinterland areas. Based on the results of the LQ analysis, the agropolitan area in Trenggalek Regency has 34 (thirteen) commodities that have an LQ value of more than 1: leaves, potatoes, mustard greens, long beans, large chilies, bird's eye chilies, green beans and chayote, c) Fruit crop subsectors: avocado, star fruit, duku, durian, guava, water guava, orange siem, large orange, mangosteen, jackfruit, papaya, rambutan, salak, sapodilla and soursop, d) Sub-sector of plantation crops: Patchouli, sugarcane, cocoa, cloves, coffee, vanilla and cottonwood. The level of public perception towards agropolitan programs is relatively poor. The level of community participation in agropolitan programs is relatively low. The intrinsic factors that have a real influence on the level of participation are income and land area, while the extrinsic factors are socialization, assistance, openness of government, program suitability and benefits. Increasing community participation can be done by improving the factors that have a real influence.