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All Journal International Journal of Electrical and Computer Engineering Jambura Journal of Electrical and Electronics Engineering Jurnal Sibermas (Sinergi Pemberdayaan Masyarakat) Jurnal Nasional Teknik Elektro dan Teknologi Informasi Empiris Jurnal Pengabdian Pada Masyarakat (EJPPM) Jurnal Pengabdian Pada Masyarakat Eldimas
Ade Irawaty Tolago
Prodi Teknik Elektro Universitas Negeri Gorontalo
Agriculture, Biological Sciences & Forestry Humanities Biochemistry, Genetics & Molecular Biology Computer Science & IT Control & Systems Engineering Economics, Econometrics & Finance Education Electrical & Electronics Engineering Energy Engineering Languange, Linguistic, Communication & Media Medicine & Pharmacology Public Health Social Sciences

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Journal : International Journal of Electrical and Computer Engineering

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Design of Digital Parity Generator Layout Using 0.7 micron Technology Wahab Musa; Sri Wahyuni Dali; Ade Irawaty Tolago
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 5: October 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (359.182 KB) | DOI: 10.11591/ijece.v8i5.pp3550-3559

Abstract

The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of design rules and verify the desired functionality gradually. The results show that the circuit has functioned well as an odd parity generator. The simulation results obtained with loads CL = 25 fF, tpLH = 2nS and tpHL = 1.46 nS indicate that tp = 1.73nS or operating frequency of 578 MHz. The integrated digital parity generator circuit using transmission gate has a size of 14758 um2 (78.5 um x188 um), consisting of 74 gates.
Co-Authors Amiruddin Y Dako Arifin Matoka Cristoper Elchrisa Ikhsan Hidayat Ilham Amu Iskandar Zulkarnain Nasibu Jumiati Ilham Lanto Kamil Amali Lanto Mohamad Kamil Amali Maharani R.P. Syafii Muhammad Yasser Arafat Rahmad Dedi Rianto Dako Rahmat D.R. Dako Rahmat Deddy Rianto Dako Sardi Salim Sri Wahyuni Dali Sri Wahyuni Dali Syahrir Abdussamad Taufiq Ismail Yusuf Wahab Musa Wrastawa Ridwan Yahja Igirisa Yasin Mohamad Zainudin Bonok