Article Per Year (5 Year)
p-Index From 2019 - 2024
1.152
P-Index
This Author published in this journals
All Journal Jurnal Ilmiah Teknologi dan Rekayasa UG Journal Seminar Nasional Informatika (SEMNASIF) Seminar Nasional Teknologi Informasi Komunikasi dan Industri JEEMECS (Journal of Electrical Engineering, Mechatronic and Computer Science) Applied Research and Smart Technology (ARSTech) Prosiding Seminar Nasional Pengabdian Kepada Masyarakat Jurnal Rekayasa elektrika
Erma Triawati Christina
Universitas Gunadarma
Humanities Automotive Engineering Civil Engineering, Building, Construction & Architecture Computer Science & IT Control & Systems Engineering Economics, Econometrics & Finance Education Electrical & Electronics Engineering Energy Engineering Environmental Science Health Professions Industrial & Manufacturing Engineering Materials Science & Nanotechnology Mathematics Physics Public Health Other

Published : 11 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 11 Documents
Search

 1   2 
Desain Layout 1-Stage ADC Pipeline 80Msps dengan Mentor Graphics 0,35µm untuk Aplikasi Kamera Kecepatan Tinggi Hamzah Afandi; Erma Triawati Ch.; Atit Pertiwi
Jurnal Rekayasa Elektrika Vol 10, No 2 (2012)
Publisher : Universitas Syiah Kuala

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.17529/jre.v10i2.141

Abstract

Design layout 1-stage pipeline is part of the 8-stage pipeline 80 Msps ADC. Layout 1-stage pipeline consists of 3 units : op-amp, switch capacitor, precision comparator with latch. Pipeline ADC works gradually and requires synchronization of digital output 8 stage by using a unit delay circuit (D-FF). Pipeline ADC requires pulse rate (clock) generator to support its work. Units OP-AMP transconductance CMOS components designed with the correct specification ADC applications with capacitive loads, with a large input impedance and minimize noise. The precision comparator has Vos (offset voltage) approximately equal to 0V. The capacitor switch designs use NMOS switch as a switch for the sampling and multiplying. In the sampling phase and multiplying processes, the ADC requires a clock pulse with a non-intersect mode (lapping). The width of non-overlapping period was adjusted to the time of constance in the sampling process and multiplying. The total number of each pulse period equal to 12.5 ns or equal to the frequency of 80MHz. In the 1-stage layout an additional correction capacitor was required to correct residual voltage. The total area of the layout 1-stage pipeline ADC is 1-bit 200 μm x 98μm.
Co-Authors Ali Akbar Aryanto Widigdo Atit Pertiwi Benny Indrawan, Benny Bertalya Bertalya Desy Kristyawati Devy Hellystia Dimas Mahesa Muharom Hamzah Afandi Kurnia Bayu Samiaji Lestari Octavia Libratyan Jhon Ngalimin Lilis Setyowati Muhamad Abdul Aziz Muhammad Taufik Mulyadi Nurlaila Nurlaila Risnawati Risnawati Sandhi Prajaka Vega Valentine Veronica Ernita Kristianti