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All Journal International Journal of Science and Engineering (IJSE) Jurnal Ilmiah Informatika Komputer Prosiding KOMMIT Prosiding Semnastek Jurnas Nasional Teknologi dan Sistem Informasi InfoTekJar : Jurnal Nasional Informatika dan Teknologi Jaringan Jurnal Ilmiah KOMPUTASI Justek : Jurnal Sains Dan Teknologi Kilat Journal of Applied Computer Science and Technology (JACOST) Engineering, Mathematics and Computer Science Journal (EMACS) Jurnal INFOTEL
Bheta Agus Wardijono
STMIK Jakarta STI&K
Automotive Engineering Civil Engineering, Building, Construction & Architecture Computer Science & IT Control & Systems Engineering Decision Sciences, Operations Research & Management Education Electrical & Electronics Engineering Energy Engineering Industrial & Manufacturing Engineering Mathematics

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Journal : Kilat

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Analysis and Design of CRC-32 IEEE 802.3 Generator for 8 Bit Data Using VHDL Aprilia Putri Dewanty; Bheta Agus Wardijono
KILAT Vol 11 No 1 (2022): KILAT
Publisher : Sekolah Tinggi Teknik - PLN

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.33322/kilat.v11i1.1536

Abstract

In the communication system to achieve better quality data transmission required a method that can detect errors and correct errors. Cyclic Redundancy Check (CRC) is one of the methods used to perform data transmission on data link layer that can detect errors. CRC-32 is used to error-checking on Ethernet or implemented to IEEE 802.3. CRC generator in this research use CRC-32 IEEE 802.3 with 8 bit data width. This research can be implemented in the field of Electrical Engineering, especially in the telecommunications section, namely Ethernet which functions for transfer files and data via a computer network. CRC here has a role to prevent data changes caused by noise during the transmission process. The methods used in this design is modulo-2 division parallel circuit. This design is expected to use a simple schematic circuit, less noise and less resources. Testing is done by matching result of simulation using Xilinx ISE Simulator with implementation on Spartan 3E XC3S500E device with result of count . This research requires a resource of 223 4-input LUTs, 114 Occupied slice, 72 IOB flip flops, 114 bonded IOBs and 1 BUFGMUXs, where this research obtained resources is fewer than with previous research
Co-Authors A I Ramadhani Ahmad Ryan Rivai Andre Bertua Naibaho Aprilia Putri Dewanty Arityo Sudartanto B.U.G Pamungkas Danarko Pakuan Putra Danarko Putra Dina Anggraiini Dina Anggraini Ega Hegarini Enrico Didi Franchman F Hendajani Hana Pertiwi Haris Satria I.P Wardhani Indra Sari Kusuma Wardhana Johann Löwen LM Rasdi Rere LM Rasdi Rere Lussiana ETP Margaretha Palma Puspita Mohammad Zulkifli Lubis Muhammad Arsal Putu Wiweka Prasetyananda Rochani Ani Rozi S A Sudiro Saeful Lukman Singgih Jatmiko Sunny Arief Sudiro Vivit Ardyansah Vivit Ardyansah Y. I Chandra